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********** C-MOS SDDI-TO-DISK FORMAT CONVERTER
-TOP VIEW- 180 175 170 165 160 155 150 145 140 135 130 125
CXD9007BR(1/5) IL08
GND VDD(+3.3V)
VDD(+3.3V) GND
VDD(+3.3V) GND
GND
181
GND GND
GND GND
121
120
VDD(+3.3V) NC 185
VDD(+3.3V)
NC
115 GND
190 110 VDD(+3.3V) GND 195 105
200
GND VDD(+3.3V)
GND VDD(+3.3V)
100
205 95 GND
210 90 NC NC 215 85 VDD(+3.3V) GND
220
VDD(+3.3V) GND
VDD(+3.3V) GND
80
225
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GND
75
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230 70 VDD(+3.3V) GND 235 65 GND VDD(+3.3V) VDD(+3.3V) GND VDD(+3.3V) GND NC VDD(+3.3V) GND GND 240 VDD(+3.3V) GND GND 61
GND
1
5
10
15
20
25
30
35
40
45
GND
NC
50
55
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60
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CXD9007BR(2/5) (VDD = +3.3V) PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O -- -- I I I I O O I I I I I I I I I I I/O -- -- I/O I/O I/O I/O I/O I/O I/O -- I I I -- I I I I I I -- -- I/O I/O I/O I/O -- I/O I/O I/O I/O I/O -- -- I/O I/O I/O I/O I/O -- -- SIGNAL GND GND SCK AMC SMC SYSCS IINTD OINTD DIRR DIRW SYSA7 SYSA6 SYSA5 SYSA4 SYSA3 SYSA2 SYSA1 SYSA0 SYSD7 GND VDD SYSD6 SYSD5 SYSD4 SYSD3 SYSD2 SYSD1 SYSD0 GND RESET CK27 CK54 NC TSTMD4 TSTMD3 TSTMD2 TSTMD1 TSTMD0 RAMTES VDD GND DQA15 DQA0 DQA14 DQA1 GND DQA13 DQA2 DQA12 DQA3 DQA11 VDD GND DQA4 DQA10 DQA5 DQA9 DQA6 GND GND PIN NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 I/O -- I/O I/O O O O -- -- O O O O O -- O O O O O -- -- O O O O O -- -- O O O O I/O -- I/O I/O I/O I/O I/O -- -- I/O I/O I/O I/O I/O -- -- I/O I/O I/O I/O I/O -- O O O O -- -- SIGNAL PIN NO. I/O SIGNAL GND GND CKEB RASB AB9 AB11 GND VDD AB8 AB10 AB7 AB0 AB6 GND AB1 AB5 AB2 AB4 GND VDD AB3 TSTD0 TSTD1 TSTD2 TSTD3 TSTD4 TSTD5 TSTD6 TSTD7 TSTD8 TSTD9 TSTD10 TSTD11 TSTD12 TSTD13 TSTD14 TSTD15 ORRST OAINT VDD GND OVINT OCINT DPEND DPSYNC OUTD7 OUTD6 OUTD5 OUTD4 OUTD3 OUTD2 OUTD1 OUTD0 DPTCWE OVWE OAWE OWRST FP GND GND PIN NO. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 I/O -- -- I I I I I I I I I O O O O O O O O -- -- O O O O I O O O O O O -- -- I I I I I -- -- I I I I I O O O O O O O O O I I I -- -- SIGNAL VDD NC SPCRD7 SPCRD6 SPCRD5 SPCRD4 SPCRD3 SPCRD2 SPCRD1 SPCRD0 SPCEMP SPCHOE SPCLOE SPCHRE SPCLRE SPCWD7 SPCWD6 SPCWD5 SPCWD4 GND VDD SPCWD3 SPCWD2 SPCWD1 SPCWD0 DMAREQ BHWEN BLWEN BWRST AHWEN ALWEN AWRST NC NC IND9 IND8 IND7 IND6 IND5 VDD GND IND4 IND3 IND2 IND1 IND0 INTCWE INVRE INARE INRRST INWRST COREOE DGREN DGRRST DGOE IAINT IVINT ICINT NC VDD
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121 -- VDD DQA8 122 -- DQA7 123 O LDQMA 124 O UDQMA 125 O WEA 126 O GND 127 -- VDD 128 -- 129 O CASA 130 O CKEA 131 O RASA 132 O AA9 133 O AA11 134 -- GND 135 O AA8 136 O AA10 137 O AA7 138 O AA0 139 -- AA6 140 -- GND 141 O VDD 142 O AA1 143 O AA5 144 O AA2 145 O AA4 146 O AA3 147 O GND 148 O VDD 149 O CS0 .com 150 O CS1 151 O CS2 152 O CS3 153 O DQB15 154 O GND 155 O DQB0 156 O DQB14 157 O DQB1 158 O DQB13 159 I DQB2 160 -- VDD 161 -- GND 162 I DQB12 163 I DQB3 164 O DQB11 165 O DQB4 166 O DQB10 167 O GND 168 O VDD 169 O DQB5 170 O DQB9 171 O DQB6 172 O DQB8 173 O DQB7 174 O GND 175 O LDQMB 176 O UDQMB 177 O WEB 178 I CASB 179 -- NC 180 -- VDD
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CXD9007BR(3/5) INPUT AMC CK27 CK54 DIRR DIRW DMAREQ FP IAINT ICINT IND0 - IND9 IVINT OAINT OCINT OVINT RAMTES RESET SCK SMC SPCEMP SPCRD0 - SPCRD7 SYSA0 - SYSA7 SYSCS TSTMD0 - TSTMD4
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
TEST 27 MHz CLOCK 54 MHz CLOCK CPU INTERFACE READ ENABLE CPU INTERFACE WRITE ENABLE DMA DATA REQUEST FRAME PULSE RX CORE IC-CHIP AUDIO INTERRUPT RX CORE IC-CHIP COMMAND INTERRUPT SDDI DATA RX CORE IC-CHIP VIDEO INTERRUPT TX CORE IC CHIP AUDIO INTERRUPT TX CORE IC CHIP COMMAND INTERRUPT TX CORE IC CHIP VIDEO INTERRUPT SD RAM TEST MODE SETTING SYSTEM RESET TEST TEST SPC READ FIFO EMPTY FLAG SPC READ DATA CPU INTERFACE ADDRESS BUS CHIP SELECT TEST MODE SETTING
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INPUT/OUTPUT DQA0 - DQA15 DQB0 - DQB15 SYSD0 - SYSD7
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; SDRAM DATA PORT A ; SDRAM DATA PORT B ; CPU INTERFACE DATA BUS
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CXD9007BR(4/5) OUTPUT AA0 - AA11 AB0 - AB11 AHWEN ALWEN AWRST BHWEN BLWEN BWRST CASA CASB CKEA CKEB COREOE CS0 - CS3 DGOE DGREN DGRRST DPEND DPSYNC DPTCWE IINTD INARE INRRST INTCWE INVRE INWRST LDQMA LDQMB OAWE OINTD ORRST OUTD0 - OUTD7 OVWE OWRST RASA RASB SPCHOE SPCHRE SPCLOE SPCLRE SPCWD0 - SPCWD7 TSTD0 - TSTD15 UDQMA UDQMB WEA WEB
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SDRAM ADDRESS PORT A SDRAM ADDRESS PORT B SPC WRITE A HIGHER FIFO WRITE ENABLE SPC WRITE A LOWER FIFO WRITE ENABLE SPC WRITE A FIFO WRITE RESET SPC WRITE B HIGHER FIFO WRITE ENABLE SPC WRITE B LOWER FIFO WRITE ENABLE SPC WRITE B FIFO WRITE RESET COLUMN ADDRESS STROBE FOR PORT A COLUMN ADDRESS STROBE FOR PORT B SDRAM CLOCK ENABLE FOR PORT A SDRAM CLOCK ENABLE FOR PORT B RX CORE IC-CHIP OUTPUT ENABLE SDRAM CHIP SELECT DIAG-FIFO OUTPUT ENABLE DIAG FIFO READ ENABLE DIAG FIFO READ RESET DEPACKED END PULSE DEPACKED SYNC TX TIME-CODE WRITE ENABLE RX SDDI RECEIVING STATUS RX CORE AUDIO FIFO READ ENABLE RX CORE FIFO READ RESET RX TIME-CODE WRITE ENABLE .com RX CORE VIDEO FIFO READ ENABLE RX CORE FIFO WRITE RESET LOWER DQ MASK ENABLE FOR PORT A LOWER DQ MASK ENABLE FOR PORT B TX CORE AUDIO FIFO WRITE ENABLE TX SDDI TRANSMITTING STATUS TX CORE FIFO READ RESET DEPACKED DATA TX CORE VIDEO FIFO WRITE ENABLE TX CORE FIFO WRITE RESET ROW ADDRESS STROBE FOR PORT A ROW ADDRESS STROBE FOR PORT B SPC READ HIGHER FIFO OUTPUT ENABLE SPC READ HIGHER FIFO READ ENABLE SPC READ LOWER FIFO OUTPUT ENABLE SPC READ LOWER FIFO READ ENABLE SPC WRITE DATA TEST DATA HIGHER DQ MASK ENABLE FOR PORT A HIGHER DQ MASK ENABLE FOR PORT B SDRAM WRITE ENABLE FOR PORT A SDRAM WRITE ENABLE FOR PORT B
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CXD9007BR(5/5)
SPCRD7 - 0 SPCEMP SPCHOE SPCLOE SPCHRE SPCLRE SPCWD7 - 0 DMAREQ BHWEN BLWEN BWRST AHWEN ALWEN AWRST DPEND DPSYNC OUTD7 - 0 DPTCWE OVWE OAWE OWRST FP IND9 - 0 INTCWE INVRE INARE INRRST ORRST OAINT 183 - 190 191 192 193 194 195 196 - 199, 202 - 205 206 207 208
SPC FIFO INTERFACE
42 - 45, 47 - 51, 54 - 58, 62, 63 64 65
DQA15 - 0 LDQMA UDQMA WEA CASA CKEA RASA AA11 - 0 CS0 - 3 DQB15 - 0 LDQMB UDQMB WEB CASB CKEB RASB AB11 - 0
210 211 212 164 165 166 - 173 174 175 176 177 178 215 - 219, 222 - 226 227 228 229 230 158 159 162 163 231 232 233 234 235 236 237 238 6 7 8 9 10 11 - 18 19, 22 - 28
SDRAM INTERFACE
209
66 69 70 71 72, 73, 75 - 79, 82 - 86 89 - 92 93, 95 - 99, 102 - 106, 109 - 113 115 116 117 118 123 124 125, 126, 129 - 133, 135 - 138, 141
DISK DE-PACKING
DISK PACKING
142 - 157
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OVINT OCINT INWRST COREOE DGREN DGRRST DGOE IAINT IVINT ICINT SYSCS IINTD OINTD DIRR DIRW SYSA7 - 0 SYSD7 - 0
TEST BUS .comSELECT CORE IC CHIP INTERFACE
TSTD0 - 15 TSTMD0 - 4 RAMTES
38 - 34 39
CPU INTERFACE
CK27 CK54 RESET SCK AMC SMC
31 32 30 3 4 5
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